On DPA-Resistive Implementation of FSR-based Stream Ciphers using SABL Logic Styles
Keywords:DPA attack, Stream cipher, Grain v.1, Trivium, SABL, Standard CMOS
AbstractThe threat of DPA attacks is of crucial importance when designing cryptographic hardware. This contribution discusses the DPA-resistant implementation of two eSTREAM finalists using SABL logic styles. Particularly, two Feedback Shift Register (FSR) based stream ciphers, Grain v.1 and Trivium are designed in both BSim3 130nm and typical 350nm technologies and simulated by HSpice software. Circuit simulations and statistical power analysis show that DPA resistivity of SABL implementation of both stream ciphers has a major improvement. The paper presents the tradeoffs involved in the circuit design and the design for performance issues.
P. C. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Advances in Cryptology - CRYPTO'99, Springer-Verlag, LNCS Vol. 1666, pp. 388-397, 1999.
Ch. Rechberger and E. Oswald, "Stream Ciphers and Side-Channel Analysis" In SASC 2004 - The State of the Art of Stream Ciphers, Brugge, Belgium, Workshop Record, pp. 320-326, Oct. 14-15, 2004.
J. Lano, N. Mentens, B Preneel, and I. Verbauwhede, "Power Analysis of Synchronous Stream Ciphers with Resynchronization Mechanism" In SASC 2004 - The State of the Art of Stream Ciphers, Brugge, Belgium, Workshop Record, pp. 327-333, Oct. 14-15, 2004.
W. Fischer, B. M. Gammel, O. Kniffler, J. Velton, "Differential Power Analysis of Stream Ciphers," Topics in Cryptology - CT-RSA 2007, Springer-Verlag, LNCS, Vol. 4377, pp. 257-270, 2007.
M. Hell, Th. Johansson, A. Maximov, andW. Meier, "Grain - A Stream Cipher for Constrained Environments," 2006, eSTREAM project website.
C. De Canniere, and B. Preneel, "Trivium Specifications," 2005, eSTREAM project website.
T. Seko, A. Nakamura, and T. Kikuno, "Measurement of glitches based on variable gate delay model using VHDL simulator," Asia-Pacific Conference on Circuits and Systems, Nov. 1998, PP. 767 - 770. http://dx.doi.org/10.1109/apccas.1998.743934
B. Gierlichs et al., "Susceptibility of eSTREAM Candidates towards Side Channel Analysis," SASC 2008, Switzerland, Feb. 13-14, 2008, Workshop Record, pp. 320 - 326.
K. Tiri, and I. Verbauwhede, "Charge recycling sense amplifier based logic: securing low power security ICs against DPA" 30th European Conference on Solid-State Circuits, 21-23 Sept. 2004, pp. 179 - 182. http://dx.doi.org/10.1109/ESSCIR.2004.1356647
K. Tiri, M. Akmal, and I. Verbauwhede, "A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards," 28th European Solid State Circuits Conference, IEEE Press, pp. 403 - 406, 24-26 Sep. 2002.
S. Mangard, E. Oswald, and T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards, Springer, 2007.
S. Babbage et. al., The eSTREAM Portfolio, April 2008, eSTREAM project website.
R.E. Atani,W. Meier, S. Mirzakuchaki, and S.E.Atani, "Design and Implementation of DPA Resistive Grain- 128 Stream Cipher Based on SABL Logic", International Journal of Computers, Communications & Control, Vol. III (supl. issue), pp. 293 - 298, 2008.
R.E. Atani, W. Meier, S. Mirzakuchaki, and S.E.Atani, "Design and simulation of a DPA resistive circuit for Trivium stream cipher based on SABL styles" Mixdes 2008, 19-21 June. 2008, pp. 203 - 208.
K. Tiri, and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation" DATE 2004, 2004, pp. 246-251.
M. Bucci, L. Giancane, R.o Luzzi, and A. Trifiletti, "Three-Phase Dual-Rail Precharge Logic" In Cryp- tographic Hardware and Embedded Systems CHES 2006, Vol. 4249 of LNCS, Springer-Verlag, 2006, pp. 232-241.
T. Popp, and S. Mangard, "Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints" In Cryptographic Hardware and Embedded Systems CHES 2005, Vol. 3659 of LNCS, Springer, 2005, pp. 172-186.
Z. Chen, and Y. Zhou, "Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage," In Cryptographic Hardware and Embedded Systems CHES 2006, Vol. 4249 of LNCS, Springer- Verlag, 2006, pp. 242-254.
D. Suzuki, and M. Saeki, "Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style" In Cryptographic Hardware and Embedded Systems CHES 2006, Vol. 4249 of LNCS, Springer-Verlag, 2006, pp. 255-269.
P. Schaumont, and K. Tiri, "Masking and Dual-Rail Logic Dont Add Up," In Cryptographic Hardware and Embedded Systems CHES 2006, Vol. 4249 of LNCS, Springer-Verlag, 2006, pp. 95-106.
B. Gierlichs, "DPA-Resistance Without Routing Constraints?" In Cryptographic Hardware and Embedded Systems CHES 2006, Vol. 4249 of LNCS, Springer-Verlag, 2006, pp. 107-120.
ONLINE OPEN ACCES: Acces to full text of each article and each issue are allowed for free in respect of Attribution-NonCommercial 4.0 International (CC BY-NC 4.0.
You are free to:
-Share: copy and redistribute the material in any medium or format;
-Adapt: remix, transform, and build upon the material.
The licensor cannot revoke these freedoms as long as you follow the license terms.
DISCLAIMER: The author(s) of each article appearing in International Journal of Computers Communications & Control is/are solely responsible for the content thereof; the publication of an article shall not constitute or be deemed to constitute any representation by the Editors or Agora University Press that the data presented therein are original, correct or sufficient to support the conclusions reached or that the experiment design or methodology is adequate.