Analytical Model For a MultiprocessorWith Private Caches And Shared Memory
Keywords:
Invalidate cache-coherence protocol, queuing system, discrete transformAbstract
We develop an analytical model of multiprocessor with private caches and shared memory and obtain the following results: the instantaneous state probabilities and the steady-state probabilities of the system. Both transient behaviour and equilibrium can be studied and analyzed. We showed that results can be applied to determine the output parameters for both blocking and non-blocking caches.References
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