VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes
Keywords:3GPP, interleaver, reconfigurable, turbo codes.
Interleaving along with error correction coding is an effective way toÂ deal with different types of error in digital data communication. Error burst due toÂ multipath fading and from other sources in a digital channel may be effectively combatedÂ by interleaving. Normally the interleaver / deinterleaver pair is often designedÂ as reconfigurable architectures able to deal with requirements of large data lengthÂ variability found in the newest communication standards. In this work reconfigurableÂ interleaver architecture for the turbo decoder in 3rd Generation Partnership ProjectÂ (3GPP) standard is presented. The interleaver is a key component of radio communicationÂ systems. Using conventional design methods, it consumes a large part ofÂ silicon area in the design of turbo encoder and decoder. The proposed interleaverÂ utilizes the algorithmic level hardware simplifications and generates 100 manage theÂ ow of data streams to achieve very low cost solution. The proposed technique reducesÂ consumption of FPGA resources to a large extent compared with existing state-ofthe-art interleaver for turbo codes. The proposed architecture con- sumes only 4856Â logic elements by hardware optimization.
3rd Generation Partnership Project (3GPP) TSG-RAN, "Multiplexing and Channel coding," Release 4, Version 4.2.0, Sept. 2001.
C. Berrou, A. Glavieux, and P. Thitimajshima, "Near-Shannon Limit Error-Correcting Coding and Decoding : Turbo Codes ", Proceedings of ICC, Geneva,Switzerland, 1993,pp.1064-1070.
C. Berrou, A. Glavieux, and P. Thitimajshima., "Near Shannon limit error correcting coding and decoding:Turbo codes. Proceedings of the IEEE International Conference on Commun, Geneva, Switzerland, May 2003.
M Valenti, "Iterative Detection and Decoding of Wireless Communications, Ph.D thesis, Virginia Polytechnic and State University, July 1999.
University of South Australia, Institute for Telecommunications Research, Turbo coding Research group, http://www.itr.unisa.edu.
Rizwan Asghar and Dake Liu, "Multimode Flex-Interleaver Core for Baseband Processor Platform", Journal of Computer Systems, Networks, and Communications Volume 2010, Article ID 793807,pp.1-16,2010.
Rizwan Asghar and Dake Liu, "Towards radix4,parallel interleaver design to support high throughput turbo decoding for reconfigurability " 33rd IEEE SARNOFF symposium, Princeton,New Jersey, USA, pages.1-5, April,2010.
"3rd Generation Partnership Project, Technical Specification Group Radio Access Network; Multiplexing and Channel Coding",Release 6, 3GPP TS 25.212 v6.0.0 (2003-12).
G.R.Blakley, " A Computer Algorithm for Calculating the Product A*Bmod M", IEEE Trans. On Comp, Vol.C-32, No.5, pp.497-500, May 1983.
Rizwan Asghar and Dake Liu "Very low cost Configurable Hardware Interleaver for 3G turbo decoding ", 3rd International Conference on Information and Communications Technologies Theory to Applications, ICTTA 2008, Damascus, Syria, pp. 1-5.
HÃ©ctor Borrayo- Sandoval, R. Parra-Michel, Luis F.GonzÃ¡lez-PÃ©rez, Fernando Landeros Printzen Claudia Feregrino-Uribe, "Design and Implementation of a Configurable interleaver/deinterleaver for Turbo Codes in 3GPP Standard ",In the proceedings of IEEE International Conference on Reconfigurable Computing and FPGAs 2009, Cancun, Mexico, pp.320- 325.
M. Shin and I.-C. Park, " Processor - based turbo interleaver for multiple third generation wireless standard" IEEE Commun. Lett., Vol. 7, no. 5, pp. 210 - 212, May 2003. http://dx.doi.org/10.1109/LCOMM.2003.812176
Z. Wang and Q. Li, "Very low-complexity hardware interleaver for turbo decoding ",IEEE Trans.on Circuits and Sys.- II: Vol.54, no. 7, pp. 636 - 640, July 2007.
Carlos R.SÃ¡nchez, R. Parra-Michel and M.E GuzmÃ¡n-Renteria, "Design and implementation of a multi-standard interleaver for 802.11a, 802.11n, 802.16e & DV standards", International Conference on Reconfigurabl Computing and FPGAs, ReConFig 2008, Cancun, Mexico, pp. 379 - 384.
P.Ampadu and K. Kornegay, "An efficient hardware interleaver for 3G turbo decoding", Proceedings of Radio and Wireless Conference,RAWCON'03, Boston, pp.199-201,2003.
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